The increasing demand for high-speed and energy-efficient Digital Signal Processing (DSP) systems has led to the development of optimized Very Large Scale Integration (VLSI) architectures. This paper presents the design and simulation of a 32-bit Parallel Self-Timed Adder (PASTA) architecture tailored for DSP processors. The PASTA architecture employs asynchronous logic design principles to achieve faster computation with reduced power consumption and delay compared to conventional ripple-carry or carry-lookahead adders. The proposed 32-bit VLSI design is modeled using hardware description languages (HDL) and simulated on standard EDA tools to evaluate performance parameters such as propagation delay, area utilization, and power efficiency. Simulation results demonstrate that the 32-bit PASTA architecture significantly enhances arithmetic performance, making it suitable for high-speed DSP applications including filtering, convolution, and real-time signal analysis. The study concludes that PASTA-based architectures provide an effective solution for achieving optimized speed-power trade-offs in next-generation DSP processor designs.
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