Design and Simulation of a 32 Bit PASTA Architecture for High Speed VLSI Circuits

Abstract

This paper presents the design and simulation of a 32-bit Parallel Self-Timed Adder (PASTA) architecture aimed at achieving high-speed and energy-efficient performance for Very Large Scale Integration (VLSI) circuits. The proposed architecture utilizes self-timed principles to eliminate the need for a global clock, thereby reducing power consumption and clock-skew issues common in synchronous systems. The 32-bit PASTA design incorporates modular carry propagation and parallel computation techniques to enhance speed while maintaining low latency and area efficiency. Simulation results, obtained using standard CMOS technology, demonstrate significant improvements in delay and power-delay product compared to conventional ripple carry and carry look-ahead adders. The architecture’s asynchronous operation also contributes to enhanced robustness under process, voltage, and temperature variations. The implementation shows that the 32-bit PASTA is a promising solution for high-performance arithmetic units in modern VLSI applications such as digital signal processing (DSP), microprocessors, and embedded systems.