In Now-a-Days we have more demand the Low power VLSI application. To design we are implementing of Built-In Self- Test (BIST) architecture using Verilog. We are proposed BIST architecture, in focuses on minimizing power consumption during the testing phase while maintaining high fault coverage. It leverages the capabilities of the Verilog hardware description language to model and simulate the design. The Project investigates various power reduction techniques, including test pattern compression, selective clock gating, and power-aware test scheduling, ta optimize power consumption during testing. Our project presents the design and implementation of a BIST architecture specifically tailored for low-power Very Large Scale Integration (VLSI) Applications. By implementing FPGA (Field programmable gate array) boards demonstrating the feasibility and practicality of the proposed design. The increasing demand for energy-efficient electronic devices and the proliferation of portable systems have necessitated the development of power-aware design techniques, BIST, a on chip testing technique, plays a crucial role in ensuring the quality and reliability of integrated circuits. The findings from this study can guide designers in developing energy-efficient and reliable integrated circuits, promoting sustainability, and extending battery life in portable devices. The proposed design is compatible with standard Verilog synthesis and is readily applicable to a wide range of low-power VLSI applications. This project presents a comprehensive study, design and implementation of a BIST architecture tailored for low-power VLSI applications, leveraging the Verilog hardware description language.
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