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This paper presents the design and implementation of an Enhanced Reversible Logic Gates-Based Pipelined Arithmetic Logic Unit (ALU) using Verilog and FPGA technology. The proposed ALU architecture aims to achieve high performance and efficiency by employing reversible logic gates and pipelining techniques. The design leverages the benefits of reversible logic gates, which ensure zero energy dissipation and minimize heat generation, leading to energy-efficient computing systems. The pipelined architecture enhances the throughput of the ALU by breaking down the computation into smaller stages and processing multiple instructions concurrently. Verilog Hardware Description Language (HDL) is utilized for the design and simulation of the ALU. The implementation is carried out on a Field-Programmable Gate Array (FPGA) platform, providing flexibility and scalability in hardware realization. Experimental results demonstrate the effectiveness of the proposed ALU design in terms of performance, energy efficiency, and area utilization. Compared to conventional ALU implementations, the proposed design offers significant improvements in throughput and power consumption, making it suitable for various applications requiring high-speed arithmetic and logic operations.
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Copyright © 2024, This is an open-access article distributed under the terms of the Creative Commons Attribution License (CC-BY-NY-SA). The use, distribution or reproduction in other forums is permitted, provided the original author(s) and the copyright owner(s) are credited and that the original publication in this journal is cited, in accordance with accepted academic practice. No use, distribution or reproduction is permitted which does not comply with these terms.
*Corresponding Author: B.R.Darshan, darshanbysani@gmail.com
Disclaimer: All claims expressed in this article are solely those of the authors and do not necessarily represent those of their affiliated organizations, or those of the publisher, the editors and the reviewers. Any product that may be evaluated in this article or claim that may be made by its manufacturer is not guaranteed or endorsed by the publisher.
Conflict of interest: The author declares that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.
Publisher’s note: All claims expressed in this article are solely those of the authors and do not necessarily represent those of their affiliated organizations, or those of the publisher, the editors and the reviewers. Any product that may be evaluated in this article, or claim that may be made by its manufacturer, is not guaranteed or endorsed by the publisher.
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